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Job Description
Designation: Formal Verification Engineer
Experience: 4+ Relevant in FV
Location: Bengaluru and Pune
Roles & Responsibilities :
Experience with Formal Verification (e.g., sequential equivalence checking, Security Path verification, connectivity, low power and Formal property verification).
Experience with programming languages (e.g., Python/Perl and TCL).
Experience with at least one formal verification tool (e.g., Cadence Jasper, Synopsys VC-Formal).
Expertise in property specification languages (e.g., SVA, PSL), as well as proficiency in HDLs such as System Verilog, Verilog or VHDL.
(Immediate to 30-day notice period candidates preferred)
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