Experience : 7-10 years
Number of Positions : 3
Role and Responsibilities :
· Individual contributor role with ability to perform assigned DV tasks independently
· Collaborate with other team members to perform DV activities.
Skills and Qualification :
Domain : CPU/Cache Coherency ,PCIe, SoC DV, CPU DV, NoC/NIC(Interconnects), DDR/HBM
· Demonstrate a solid understanding of the CPU/CPU Based SoC Verification.
· Must have good understanding of one or more of the following domains
o ARM v8/v9, RISC-V, x86 Architecture
o Memory Architecture(DRAM, Cache, MMU), GIC, SoC Debug Architecture
o Cache Coherent Architectures
o PCIe OSCI Layer and its functionality
o PCIe Phy, Bring up and trainin
o SoC DV, BUS Interconnects
- Understand architecture and micro-architecture specifications.
- Work closely with Architects and Logic Designers.
- Develop Unit Level and/or Subsystem Level Test plans, Coverage Plans and checker Plans needed to target zero defect post-silicon quality.
- Develop scalable Test benches in System Verilog and UVM.
- Develop Tests, Functional Coverage Models and System Verilog Assertions.
- Root cause regression failures by debugging Tests/Sequences, RTL and C++ Models.
- Maintain higher regression efficiency via Test/Coverage Grading, Compute Farm and Disk utilization, etc.
- Drive Code and Functional Coverage closure.
- Support debug of Unit RTL/Checkers at higher levels of integration such as Subsystem/Top.
- Solid understanding of Computer Architecture.
- Understanding of SoC Architecture ,micro-architecture, logic design, FSMs.
- Strong functional verification experience including Test planning, Test bench Architecture, Test/Coverage Model/Assertion Development.
- Strong debugging skills.
- Proficient in System Verilog/UVM/OVM, OOP/C++ and Python scripting.
- Previous scripting experience is desirable