AMS Verification Engineer - Verilog/System Verilog

<p>Key Responsibilities - AMS Verification<br/><br/>- Work in Analog Mixed-Signal (AMS) Verification for SoCs, subsystems, and IPs.<br/><br/>- Hands-on experience with AMS simulation environments using Cadence, Synopsys, or Mentor tools.<br/><br/>- Solid understanding of analog and mixed-signal circuits, including - comparators, op-amps, switched-cap circuits, ADCs/DACs, current mirrors, charge pumps, and regulators.<br/><br/>- Strong knowledge of Verilog, Verilog-A, Verilog-AMS, and Verilog-D for behavioral modeling.<br/><br/>- Experience in block-level and chip-level AMS verification, including top-level testbench development, self-checking testbenches, and regression suites.<br/><br/>- Exposure to SystemVerilog (SV) and UVM from an AMS perspective is a plus.<br/><br/>- Proficiency in scripting languages such as Python, Perl, TCL, or SKILL for automation.<br/><br/>- Fluency with Cadence Virtuoso-based analog design flow, including schematic capture, simulator/netlist configuration, and SPICE simulation.<br/><br/>- Ability to extract, analyze, and document simulation results and present findings in technical reviews.<br/><br/>- Familiarity with test plan development, AMS modeling, and verification methodologies.<br/><br/>- Supporting post-silicon validation and correlating measurement data with simulations.<br/><br/>- Team-oriented, proactive, and able to contribute in a multi-site development environment.</p> (ref:hirist.tech)