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Urgent! ASIC RTL Design Engineer (NOT FPGA RTL) Job Opening In Bengaluru – Now Hiring 7hillsTS

ASIC RTL Design Engineer (NOT FPGA RTL)



Job description

Key skills with hand on: ASIC,RTL Design, VLSI-SOC ,AMBA, Lint, CDC, Synopsys LintCDC/VerdiXcellium/Synopsys DC.Experience: 5 - 25 yearsWork Location: Trivandrum, Bangalore, Hyderabad, Chennai, PuneEducation: Engineering (excluding Mechanical/Civil)Detailed JD:IP RTL design targeted for SOC, Static checks, some basic protocolsExpertise in SoC subsystem/IP designExpertise in IP design, Subsystem/Cluster and SoC level integration using Verilog/System VerilogIn depth knowledge on RTL quality checks ( Lint, CDC )Knowledge of synthesis and low power is a plusGood understanding of AMBA bus protocols (AXI, AHB, ATB, APB )Good understanding of timing conceptsKnowledge of one or more of the interface protocolsPCIe/DDR/Ethernet/I2C,UART/SPIExpertise in setting up and using tools likeSpyglass Lint/CDCSynopsys DCVerdi/XcelliumUnderstanding of scripting languages like Make flow, Perl ,shell, python etc


Required Skill Profession

Semiconductor Manufacturing



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