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Urgent! Capgemini - Analog Layout Engineer Job Opening In Gurugram – Now Hiring Capgemini Technology Services India Limited

Capgemini Analog Layout Engineer



Job description

<p></p><p><b>Analog Layout Engineer</b><br/><br/></p><p>Location : Mumbai, Pune, Hyderabad, Chennai, Noida, Gurgaon, Bangalore, Gandhinagar</p><p><br/></p><p>At Capgemini Engineering, the world leader in engineering services, we bring together a global team of engineers, scientists, and architects to help the worlds most innovative companies unleash their potential.

From autonomous cars to life-saving robots, our digital and software technology experts think outside the box as they provide unique R&D and engineering services across all industries.

</p><p><br/></p><p>Join us for a career full of opportunities.

Where you can make a difference.

Where no two days are?the Description : </b></p><p><br/></p>- To work independently on block/IP levels analog layout design from schematic.<br/><br/><p></p><p>- Estimating the Area, Optimizing Floorplan, Routing and Verifications.<br/><br/></p><p>- Good at LVS/DRC debugging skills and other verifications for lower technology nodes like 5,7,10, 14nm FinFet and below.<br/><br/></p><p>- Good understanding of Matching, EM, ESD, Latch-Up, Shielding, Parasitic and short channel concepts.<br/><br/></p><p>- Familiar with EDA tools like Cadence Virtuoso Editor & Calibre RVE Good interpersonal skills and critical thinking abilities to resolve the issue technically, and Responsibilities : </b></p><p><br/></p><p>- Independently execute block/IP-level analog layout from schematics, including area estimation, floorplan optimization, routing, and layout verification.</p><p><br/></p><p>- Perform LVS (Layout vs.

Schematic) and DRC (Design Rule Check) debugging for advanced FinFET technology nodes (5nm, 7nm, 10nm, 14nm and below).<br/><br/></p><p>- Ensure layout quality by applying principles of matching, electromigration (EM), electrostatic discharge (ESD), latch-up prevention, shielding, parasitic management, and short channel effects.<br/><br/></p><p>- Utilize industry-standard EDA tools such as Cadence Virtuoso Editor and Calibre RVE for layout and verification Skills : </b></p><p><b><br/></b></p>- Analog Layout Design (Block/IP level)<br/><br/><p></p><p>- LVS/DRC Debugging<br/><br/></p><p>- FinFET Technology Node Experience (5nm, 7nm, 10nm, 14nm and below)<br/><br/></p><p>- EDA Tools<br/><br/></p><p>- Cadence Virtuoso Editor<br/><br/></p><p>- Calibre RVE<br/><br/></p><p>- Layout Optimization<br/><br/></p><p>- Area estimation<br/><br/></p><p>- Floorplanning<br/><br/></p><p>- Skills : </b></p><p><br/></p><p>- These support the primary responsibilities and enhance performance :</p><p><br/></p>- Understanding of Physical Design Concepts : (EM)</li><li>Electrostatic Discharge Short Channel Effects<br/><br/><p>- Critical Thinking & Problem Solving</p><br/><p>- Interpersonal and Communication Skills</p><br/><p>- Team Qualification : </b> Bachelor's or Master's Degree</p><p></p> (ref:hirist.tech)


Required Skill Profession

Engineers



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