Design For Testing Engineer

#Urgent_Opening_for_Canvendor#Hiring : DFT Engineer (3+ Years Experience) |Bangalore| Immediate Joiners PreferredLocation: Bangalore, IndiaExperience: 3-8 YearsNotice period: Immediate to 30daysMandatory: DFT, ATPG, Scan Insertion, EDA Tools#Key_Requirements :DFT Fundamentals including JTAG, Scan, ATPG, IEEE 1687 iJTAG, EDT ArchitectureScan Insertion using Fusion Compiler or other EDA toolsATPG Coverage Analysis and DRC clean upATPG patterns simulation and debug using SNPS VCS and Verdi toolsUnderstanding of Design for Test methodologies and DFT experience (e.G. JTAG 1149.X, IEEE 1500, IEEE 1687 iJTAG, Scan, ATPG, Memory BIST, etc.)Familiar with DFT flow and EDA tools, including Fusion Compiler, Synopsys Tmax or Mentor Testkompress/Tessent, SSN, etc.Experienced with Verilog, System Verilog, VCS simulation tool, Perl/Shell scripting, and Verilog RTL designExperience in debugging Compressed ATPG patterns, MBIST, and JTAG/1500 related issuesExperience in test failures debug to determine the root cause;
work with design engineers to resolve design defects and correct any test issuesExperience with STA constraints development, analysis for DFT modes and SDF simulationsGood communication skillsIf interested kindly share your updated CV toanushab@canvendor.com