DDR Verification: Lead the verification of DDR memory controller and PHY designs, ensuring compliance with DDR standards such as DDR3, DDR4, DDR5, and other memory interface protocols.
Testbench Development: Develop and implement scalable, reusable, and efficient verification environments and testbenches for DDR designs using SystemVerilog, UVM (Universal Verification Methodology), and other industry-standard verification methodologies.
Protocol Compliance: Ensure the DDR design meets protocol specifications, including command, data, and clock synchronization, read/write cycles, burst transfers, refresh cycles, error handling, and power management.
Verification Plan Creation: Develop detailed verification plans based on DDR specifications and requirements, ensuring full coverage of corner cases, timing, and protocol validation.
Simulation & Debugging: Run simulations and debug issues using tools such as Questa, VCS, or ModelSim, applying advanced debugging techniques such as waveform analysis, assertion-based verification, and code coverage.
Regression Testing: Set up and manage regression testing for DDR functionality to ensure continuous validation and early detection of design issues.
Verification Coverage: Achieve high functional and protocol coverage, ensuring that critical aspects of DDR design, including timing constraints, corner cases, and failure scenarios, are thoroughly verified.
Formal Verification: Implement formal verification techniques to validate key components of the DDR design, ensuring correctness in timing and data flow, and verifying the most critical operations.