Design Verification Engineer

<p>- 15+ years of experience in System Level verification using C and UVM verification<br/><br/>- Proficient in testplanning and testcase development in C/Assembly/SystemVerilog<br/><br/>- Expertise in verifying design at RTL level and gate-level simulation<br/><br/>- SoC exp should have.<br/><br/>- Good understanding of coverage analysis, performance verification and use-case verification<br/><br/>- Usage of the third party Verification IPs<br/><br/>- Experience in functional test development for post-silicon bring-up/debug<br/><br/>- Fluency with scripting languages (e.g., Make, Perl, Python, Shell); and<br/><br/>- Has worked on the project complete cycle from the Specification to Tapeout and involved in Post Silicon Validation.<br/><br/>- Exposure to the FPGA Validation and debug<br/><br/><b>Must have experience on SoC verification and high-speed protocols exp.

Like, PCIe, USB, GPIO, Slow Peripherals requirements - Soft Skills<br/><br/> Communication<br/><br/>- Able to abstract technical details.

Open to communicate with people on and off site.

Open-minded.<br/><br/>- Excellent communication skills, enjoys working in an international team across locations<br/><br/>- Very good level of spoken and written English ( at least B2 level).<br/><br/>- Strong presentation and listening skills are required Team player<br/><br/>- Committed to the team and task<br/><br/>- Helping team members, sharing knowledge Self-driven and highly motivated<br/><br/>- Self-motivated and self-dependent worker.

Embracing the task.<br/><br/>Highlight potential issues<br/><br/>- Regular reporting.

Clean and organized working style.

Able to go the extra mile Solution oriented attitude, pragmatic.

Good problem solving skills<br/><br/>- Following and improving processes<br/><br/>- Able to follow corporate reporting standards Organized, trusted, committed to a long term employment<br/><br/>- Quality awareness</p> (ref:hirist.tech)