Description
We are seeking a skilled Design Verification Engineer to join our team in India.
The ideal candidate will have 4-9 years of experience in design verification, working with digital and mixed-signal designs to ensure high-quality products through rigorous testing and validation.
Responsibilities
- Develop and execute design verification plans and test cases for digital and mixed-signal designs.
- Perform simulations and analysis to validate design functionality and performance.
- Identify and debug design issues and provide solutions to improve design robustness.
- Collaborate with cross-functional teams, including design engineers and system architects, to ensure alignment on design requirements.
- Prepare detailed documentation of verification processes and results, including test reports and compliance matrices.
- Utilize industry-standard verification tools and methodologies, including UVM, SystemVerilog, and assertions.
Skills and Qualifications
- 4-9 years of experience in design verification engineering or related field.
- Strong knowledge of digital design principles and methodologies.
- Proficient in verification languages such as SystemVerilog and VHDL.
- Experience with verification tools such as ModelSim, VCS, or Questa.
- Familiarity with UVM (Universal Verification Methodology) and testbench development.
- Understanding of RTL design and simulation.
- Ability to analyze and debug complex digital systems.
- Strong problem-solving skills and attention to detail.
- Excellent communication and teamwork skills.
Skills Required
Design Verification, Uvm, systemverilog