<p><b>Job Description :</b></p><p><p><b><br/></b></p>We are seeking an experienced Verification Engineer with strong expertise in System Verilog (SV), UVM methodology, and hands-on experience in PCIe (Gen4/Gen5) verification.
The ideal candidate should have worked on Root Complex, PCIe Controller verification and possess deep knowledge of high-speed protocols, functional verification, and test bench development.<br/><b><br/></b><b>Key Responsibilities :</b></p><p><p><b><br/></b></p>- Develop and execute test plans for PCIe Gen4/Gen5 Root Complex and Controller IP.<br/><br/>- Build, enhance, and maintain UVM-based verification environments in SystemVerilog.<br/><br/>- Create testbenches, sequences, monitors, scoreboards, and checkers for functional coverage.<br/><br/>- Perform coverage-driven verification (functional/code/branch/MC/DC) and debug failures using simulation tools.<br/><br/>- Collaborate with design and architecture teams to understand specifications and identify corner cases.<br/><br/>- Analyze protocol compliance and ensure design meets PCIe standard specifications.<br/><br/>- Run regressions, triage failures, and drive resolution in coordination with design teams.<br/><br/>- Provide technical guidance and mentor junior team members (if senior role).<br/><br/></p><p>Required Skills & Experience :<br/><br/>- Strong knowledge of System Verilog, OOP concepts, and UVM methodology.<br/><br/>- Hands-on experience in PCIe Gen4/Gen5 verification (must have worked on Root Complex and/or PCIe Controller).<br/><br/>- Experience in writing test benches, sequences, assertions, and checkers.<br/><br/>- Strong debugging skills using industry-standard simulators (e.g., VCS, Questa, Xcelium).<br/><br/>- Familiarity with protocol analyzers, traffic generators, and PCIe compliance testing.<br/><br/>- Solid understanding of verification concepts: functional coverage, constraint random testing, assertions (SVA).<br/><br/>- Good communication skills and ability to work in a collaborative environment.<br/><br/><b>Nice to Have :</b></p><p><br/></p><p>- Exposure to other high-speed protocols (CXL, Ethernet, DDR, etc.).<br/><br/>- Experience with formal verification and emulation/prototyping platforms.<br/><br/>- Knowledge of Python/Perl/Tcl scripting for automation.<br/><br/>- Familiarity with SoC-level verification.<br/><br/>Education :</p><p><br/></p><p>- Bachelor's or Master's degree in Electronics/Electrical/Computer Engineering or equivalent.</p> (ref:hirist.tech)