Design Verification Engineer - UVM/RTL Design

<p><p><b>Role :</b> Design and Verification Engineer<br/><br/><b>Experience :</b> 5+ Years<br/><br/><b>Location :</b> Bangalore<br/><br/><b>Mode :</b> Full time<br/><br/><b>Job Description :</b><br/><br/>- Develop and implement comprehensive verification plans using industry-standard methodologies (e.g., </p><p>UVM)<br/><br/></p><p>- Design and write robust verification environments (testbenches) to achieve high code coverage<br/><br/></p><p>- Utilize simulation tools (e.g., ModelSim, Cadence Incisive, Synopsys VCS) to verify RTL functionality<br/><br/></p><p>- Debug and analyze verification failures to identify the root cause of design issues<br/><br/></p><p>- Collaborate with RTL design engineers to resolve functional bugs and ensure design revisions meet verification requirements<br/><br/></p><p>- Participate in code reviews and ensure adherence to verification coding standards<br/><br/></p><p>- Stay up-to-date with the latest verification tools and methodologies<br/><br/><b>Qualifications :</b><br/><br/>- Bachelor's degree in electrical engineering, Computer Engineering, or a related field (master's degree a plus)<br/><br/></p><p>- 5 - 7 years of experience in design verification for ASICs or SoCs<br/><br/></p><p>- Strong understanding of digital design principles (combinational logic, sequential logic)<br/><br/></p><p>- Proven ability to develop and debug complex verification environments<br/><br/></p><p>- Proficiency in Verilog or VHDL with experience in verification methodologies (e.g., UVM)<br/><br/></p><p>- Experience with simulation tools and scripting languages (e.g., Python, Perl) is a plus<br/><br/></p><p>- Excellent analytical and problem-solving skills<br/><br/></p><p>- Strong communication and collaboration skills to work effectively in a team environment</p><br/></p> (ref:hirist.tech)