Design Verification Engineer - UVM/System Verilog

<p><p><b>About the Role :</b><br/><br/>We are seeking an experienced Design Verification Engineer to join our team and work on the verification of complex IP or subsystem blocks.

The ideal candidate should have strong expertise in SystemVerilog, UVM methodology, and verification of high-performance interconnects and protocols.<br/><br/><b>Key Responsibilities :</b><br/><br/>- Execute IP or subsystem verification of complex design blocks<br/><br/>- Develop verification plans, environments, and testbenches using SystemVerilog and UVM<br/><br/>- Perform functional verification and ensure robust coverage metrics<br/><br/>- Debug and resolve verification issues efficiently<br/><br/>- Collaborate with design teams for seamless integration and verification closure<br/><br/><b>Required Skills :</b><br/><br/>- Proficiency in SystemVerilog (SV), UVM, assertions, and coverage-driven verification<br/><br/>- Strong experience in Fabric/NOC/Interconnect block verification<br/><br/>- Knowledge of AMBA suite protocols (AXI/ACE), PCIe, CXL, interrupt handling, and power management<br/><br/><b>Good to Have :</b><br/><br/>- Experience in coherent traffic verification<br/><br/><b>Who Were Looking For :</b><br/><br/>- Strong problem-solving and debugging skills<br/><br/>- Excellent communication and teamwork abilities<br/><br/>- Ability to work independently and deliver high-quality verification</p><br/></p> (ref:hirist.tech)