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Urgent! Design Verification Lead - SoC/System Verilog Job Opening In Bengaluru – Now Hiring SEMI LEAF

Design Verification Lead SoC/System Verilog



Job description

<p>Responsibilities :</p><p><br/></p><p>- Author verification plans from specs and micro-architecture; build reusable UVM environments from scratch at subsystem or SoC level.<br/><br/>- Develop constrained-random and directed tests, scoreboards, checkers, coverage models, and assertions (SVA).<br/><br/>- Drive coverage closure (functional, code, assertion), root-cause complex bugs, and work closely with RTL, architecture, and DFT.<br/><br/>- Enable SoC-level verification including interface/IP integration, coherency, low-power modes, resets/boot, and performance validation.<br/><br/>- Support silicon bring-up and correlation of failures to pre-silicon environments.<br/><br/>Must-have qualifications :<br/><br/>- 8+ years of hands-on ASIC verification experience (FPGA or emulation-only work does not count toward the 8 years).<br/><br/>- Multiple production ASIC tapeouts with ownership of SoC or subsystem-level UVM environments and coverage closure.<br/><br/>- Expert in SystemVerilog, UVM, SVA, and constrained-random methodologies; strong debug skills with waveforms and logs.<br/><br/>- Experience verifying standard interfaces and complex subsystems (AXI/ACE, DDR/PCIe, coherency, memory/interrupt fabric, power states).<br/><br/>- Strong testplanning, stimulus strategy, checkers/scoreboards, and closure discipline.<br/><br/>Nice to have :<br/><br/>- Low-power verification (UPF-aware), performance/latency verification, firmware-aware verification, emulation acceleration as a complement to UVM.<br/><br/>- Scripting (Python/Tcl) used to enhance hands-on verification, not in lieu of it.<br/><br/>Discounted / not counted experience :<br/><br/>- Regression running/triage-only roles or lint/CDC-only roles are discounted.<br/><br/>- IP-level-only verification without subsystem/SoC integration responsibility is insufficient.<br/><br/>- Primarily management, methodology-only, or tool-maintenance roles without recent hands-on testbench development will be discounted.<br/><br/>- FPGA-based validation experience does not count toward the minimum.</p> (ref:hirist.tech)


Required Skill Profession

Computer Occupations



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