Design Verification (RISC-V) 4+years

RISC-V Verification:

Lead the verification of RISC-V processor cores, ensuring compliance with the RISC-V ISA specifications (e.g., RV32/64/128, Privileged Architecture, Custom Extensions).
Testbench Development:

Design, implement, and maintain reusable, scalable, and efficient testbenches using SystemVerilog, UVM (Universal Verification Methodology), and other industry-standard verification methodologies.
Instruction Set Architecture (ISA) Compliance:

Verify that the RISC-V cores and components comply with the RISC-V ISA and its extensions (e.g., M, A, F, D, C).

Ensure correct execution of instructions, exception handling, and interrupt processing.
Functional Coverage:

Ensure complete functional coverage of all RISC-V operations, corner cases, and compliance with architectural requirements.
Verification Plan Creation:

Develop detailed verification plans and strategies based on RISC-V specifications, ensuring comprehensive validation of all design features and functional requirements.