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Urgent! DFT Engineers (Lead & Mid-Level) Job Opening In Hyderabad – Now Hiring Cyient Semiconductors



Job description

Lead & Mid-Level DFT Engineers – Multiple Openings


Positions:

  • Mid-Level: 4–10 years experience
  • Lead: 10+ years experience


About the Role:

Are you ready to drive the development of Design-for-Test (DFT) strategies for advanced SoCs?

We are looking for Lead and Mid-Level DFT Engineers to contribute to and shape DFT methodologies from concept to silicon, working on cutting-edge process nodes (14nm and below).

You’ll collaborate closely with cross-functional design teams, leverage the latest EDA tools, and play a pivotal role in ensuring testability, yield, and quality for high-performance silicon products.

If you are passionate about solving complex challenges, mentoring teams, and leading innovative testing solutions, this is the role for you.


Key Responsibilities:

  • Lead/execute DFT architecture, planning, implementation, and verification for complex SoCs and ASICs.
  • Perform Scan Insertion, Compression, ATPG, MBIST, and Boundary Scan (JTAG, IEEE 1149.x) .

  • Implement and validate DFT features using Synopsys, Cadence, Mentor Graphics , or equivalent tool suites.

  • Own DFT simulation, test vector generation, and fault coverage analysis .

  • Ensure robust silicon tape-outs with high test coverage at advanced nodes (14nm and below).

  • Collaborate on SoC-level integration, synthesis, and STA .

  • Automate DFT flows using Tcl, Perl, or Python to improve efficiency and reliability.

  • Mentor junior engineers, conduct technical reviews, and manage project deliverables (Lead level).

  • Interface with internal teams for technical alignment and support.


Required Skills & Qualifications:

Mid-Level DFT Engineer:

  • Experience: 4–10 years in DFT for complex SoC/ASIC environments
  • Hands-on with Synopsys DFTMax/TetraMax or Cadence tools
  • Quick joiners preferred; ability to close interviews and join immediately
  • Strong scripting skills in Tcl, Perl, or Python

Lead DFT Engineer:

  • Experience: 10+ years in DFT, with hands-on ownership of full-chip DFT flows
  • Expertise in Synopsys DFTMax or TetraMax
  • Strong leadership, mentoring, and project management capabilities

General Skills (Both Levels):

  • Strong understanding of Scan/Compression & ATPG, MBIST/BIST, Boundary Scan/JTAG (IEEE 1149.x)
  • Experience with DFT bring-up and production test on silicon
  • Excellent communication skills and proven ability to work with cross-functional teams


Why Join Us:

  • Work on state-of-the-art SoCs and advanced process nodes
  • Collaborate with high-performing, innovative engineering teams
  • Take ownership of critical DFT initiatives and silicon success
  • Opportunity to mentor and grow your career in a cutting-edge technology environment


Interested or know someone great?

Send your resume to or reach out via Call/WhatsApp at .


Required Skill Profession

Engineering Services,semiconductor Manufacturing,appliances, Electrical, And Electronics Manufacturing



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