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Urgent! Field-Programmable Gate Arrays Engineer Job Opening In Bengaluru – Now Hiring ACL Digital

Field Programmable Gate Arrays Engineer



Job description

FPGA Design Engineer

Experience : 4 years

Location : Bangalore



Job Description:•4+ years of experience in PL design creation.

• Working experience on Vivado project flows.

• Working knowledge on Xilinx/AMD devices.

• Working experience on Linux environment.

• Working experience on any scripting language (TCL/Shell/Python).

• Good to have experience in RTL coding.

• Good to have experience in Vitis flows.

Basic Job Deliverable:Responsible for creating PL designs using Vivado.

Responsible for maintaining IDF regressions for different device families.

Responsible for creating and updating XAPP documents.

Responsible for creating and maintaining ROAST regressions (based on Python) for BFR scripts.


Interested,please share your updated resume to janagaradha.n@acldigital.com


Required Skill Profession

Engineers



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