FPGA Designer - VHDL/Verilog

<p><p><b>Job :</b><br/><br/>- Design, architect, and develop FPGA RTL (VHDL/Verilog) logic and subsystems for high-speed serial protocols.<br/><br/>- Address FPGA design challenges such as CDC, multi-clock domains, timing closure, and SerDes-related issues.<br/><br/>- Drive timing closure and optimization using FPGA synthesis and implementation tools (Xilinx Vivado).<br/><br/>- Debug and validate FPGA and board-level issues, ensuring robust high-speed interface performance.<br/><br/>- Collaborate with global R&D teams to deliver production-ready FPGA solutions.<br/><br/>- Leverage AI-assisted tools (e.g., GitHub Copilot, LLM-based aids) to accelerate RTL development and productivity.<br/><br/><b>Requirements :</b><br/><br/>- 7+ years of FPGA design and development experience.<br/><br/>- Strong expertise in any high-speed serial protocols (PCIe, NVMe, CXL preferred; others such as Ethernet, USB 3.x/USB4, SATA, SAS, InfiniBand, DisplayPort, HDMI, or MIPI M-PHY also acceptable).<br/><br/>- Proven skills in high-speed FPGA design, including CDC handling, timing closure, and interface validation.<br/><br/>- Hands-on experience with FPGA synthesis/implementation tools (Xilinx Vivado: synthesis, place-and-route, timing closure, on-board debug).<br/><br/>- Experience with FPGA simulation tools (ModelSim, Questa, VCS, or Vivado Simulator) for design validation.<br/><br/>- Degree in Electrical or Electronics Engineering from Tier-1 colleges (IITs, NITs, or equivalent) preferred.<br/><br/>- Proactive problem-solver with enthusiasm, energy, and a hands-on approach.</p><br/></p> (ref:hirist.tech)