Halma India - Design Verification Engineer - UVM/System Verilog

<p><p><b>Job Description :</b></p><p><br/></p><p><p><b>Key Responsibilities :</b></p><p><br/></p>- Execute IP or subsystem verification of complex design blocks<br/><br/></p><p>- Develop verification plans, environments, and testbenches using SystemVerilog and UVM<br/><br/></p><p>- Perform functional verification and ensure robust coverage metrics<br/><br/></p><p>- Debug and resolve verification issues efficiently<br/><br/></p><p>- Collaborate with design teams for seamless integration and verification Skills :</b></p><p><br/></p>- Proficiency in SystemVerilog (SV), UVM, assertions, and coverage-driven verification<br/><br/></p><p>- Strong experience in Fabric/NOC/Interconnect block verification<br/><br/></p><p>- Knowledge of AMBA suite protocols (AXI/ACE), PCIe, CXL, interrupt handling, and power to Have :</b></p><p><br/></p>- Experience in coherent traffic Were Looking For :</b></p><p><br/></p>- Strong problem-solving and debugging skills<br/><br/></p><p>- Excellent communication and teamwork abilities<br/><br/></p><p>- Ability to work independently and deliver high-quality verification</p><br/></p> (ref:hirist.tech)