Should be able to handle Full chip hashtag
Added advantage for #Innovus with Minimum 4 years
#PnR (timing/congestion/CTS issues), understanding of hashtag
#IO ring,
#package support, multi hashtag
#voltage design.
๐ธDeep understanding of the concepts related to hashtag
#synthesis, place & route, hashtag
#CTS, timing convergence, IR/EM checks and signoff DRC/LVS closure.
๐ธResponsible for independent planning and execution of all aspects of physical design including
#floor_planning,
#place_and_route,
#Clock_Tree_Synthesis, Clock Distribution, extraction, Timing closure, Power and Signal Integrity Analysis, hashtag
#Physical_Verification,
#DFM.
๐ธMust have participated in all stages of the design (floor planning, placement, CTS, routing, physical verification,
#IREM).
๐ธWell versed with the timing closure (#STA), timing closure methodologies
Good Understanding of DRC, LVS,
#ERC and PERC rule files for lower tech node layout verification.
๐ธExperience in
#lower tech
#node (<
7nm).
๐ธGood automation skills in hashtag
#PERL,
#TCL and EDA tool-specific scripting.
๐ธAble to take complete ownership for Block/sub-system for complete execution cycle.
๐ค๐๐ฎ๐น๐ถ๐ณ๐ถ๐ฐ๐ฎ๐๐ถ๐ผ๐ป
๐ธBE/BTECH/MTECH in EE/ECE with proven experience in hashtag#ASIC Physical Design.
๐ธDetailed knowledge of EDA tools and flows, Fusion compiler based RTL2GDS flow is desired
๐๐ ๐ฝ๐ฒ๐ฟ๐ถ๐ฒ๐ป๐ฐ๐ฒ: 4+ Years
๐๐ผ๐ฐ๐ฎ๐๐ถ๐ผ๐ป: ๐๐ฎ๐ป๐ด๐ฎ๐น๐ผ๐ฟ๐ฒ.