Incise Infotech - Static Timing Analysis Engineer - VLSI

<p><p><b>Immediate Joiners Preferred</b><br/><br/><b>About the Role : </b><br/><br/>Incise Infotech Limited is expanding its VLSI Design team and is looking for skilled Static Timing Analysis (STA) Engineers to contribute to high-performance chip design projects.<br/><br/>This role is ideal for engineers passionate about full-chip timing closure, constraint development, and timing verification in advanced technology nodes.<br/><br/><b>Key Responsibilities : </b><br/><br/>- Perform Static Timing Analysis at both block and full-chip levels using industry-standard tools such as PrimeTime or Tempus<br/><br/>- Analyze and debug setup, hold, transition, and other timing violations<br/><br/>- Work closely with RTL, Synthesis, and Physical Design (PD) teams to drive timing closure<br/><br/>- Develop, validate, and manage SDC constraints for various design stages<br/><br/>- Ensure timing sign-off readiness by generating and reviewing timing reports<br/><br/>- Innovate and automate STA flows for improving efficiency and quality of results<br/><br/>- Collaborate with design teams to support tape-out schedules and quality metrics<br/><br/>- Perform PPA (Power, Performance, Area) analysis and support ECO timing closure<br/><br/>- Support multiple projects by providing STA inputs during design reviews<br/><br/><b>Required Skillsets</b><br/><br/>- Hands-on experience in STA tools like PrimeTime, Tempus, etc.<br/><br/>- Strong understanding of timing concepts, clock domains, and signal integrity<br/><br/>- Expertise in writing and debugging SDC constraints<br/><br/>- Solid knowledge of CMOS, VLSI design flows, and timing closure methodologies<br/><br/>- Proficient in TCL scripting and automation of STA reports and flows<br/><br/>- Familiarity with synthesis, floorplanning, and physical design interactions<br/><br/>- Experience with advanced technology nodes (e.g., 7nm, 16nm, 28nm) is a plus<br/><br/>- Good communication and problem-solving skills<br/><br/>- Ability to work independently and collaboratively in a fast-paced environment</p><br/></p> (ref:hirist.tech)