Requirements
- 3-15 years of hands-on experience in timing analysis
- Experience in doing SoC level timing analysis
- Should be familiar with timing analysis for hierarchical designs
- Familiarity with different types of interfaces like PCIe, SATA, USB, DDR etc.
- Worked on technology nodes 5nm and below
- Proficiency in industry standard STA tools (Tempus /PrimeTime)
- Good scripting skill in Tcl and Python
- Familiarity with different physical design tools – preferably Cadence Innovus
Qualification : BTech/MTech from a reputed university.