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Urgent! Memory Layout Engineer Job Opening In Bengaluru – Now Hiring BITSILICA

Memory Layout Engineer



Job description

Exp: 3 to 8 YearsLocation: Bangalore Notice: Immediate - 15 days✅ Memory Leafcell layout library design from scratch including top level integration.✅ Good knowledge on different types of memory architectures.✅ Good knowledge in optimized layout design for better performance.✅ Sound knowledge & hands on experience in Finfet technology, layout design and DRC limitations.✅ Proficient in physical verification flow & debug, like DRC, LVS, ERC, Boundary conditions.✅ Proficient in Cadence Virtuoso layout editor and Calibre physical verification flow


Required Skill Profession

Engineers



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