<p><p><b>Principal CPU Design Verification Engineer </b><br/><br/>We are seeking an experienced verification engineer to lead verification efforts of complex CPU and related subsystems based on the open-source RISC-V architecture.
The right candidate will have deep technical expertise combined with exceptional leadership skills.<br/><br/><b>Responsibilities : </b><br/><br/></p><p>- Lead end-to-end verification from complex CPU sub-units up to CPU clusters, partnering with architecture and design teams<br/><br/></p><p>- Develop verification infrastructure components including test-benches, scoreboards, and stimulus generators<br/><br/></p><p>- Develop and execute comprehensive verification plans for units and features<br/><br/></p><p>- Implement functional coverage models<br/><br/></p><p>- Debug designs in simulation, prototyping platforms, and silicon<br/><br/></p><p>- Continuously drive methodology improvements to improve efficiency<br/><br/></p><p>- Lead senior and junior engineers as a team to accomplish successful projects<br/><br/><b>Minimum Qualifications : </b><br/><br/></p><p>- Bachelors or Masters degree in electrical, computer engineering or related field<br/><br/></p><p>- BS+10 years or MS+12 years of industry experience successfully delivering CPU implementations<br/><br/><b>Skills & Qualifications Required : </b><br/><br/></p><p>- System Verilog verification development experience<br/><br/></p><p>- Testbench construction using UVM or analogous methodologies<br/><br/></p><p>- Scoreboards and stimulus generators for complex units<br/><br/></p><p>- Strong background in one or more common CPU ISAs. x86, ARM, MIPS, RISC-V, etc.<br/><br/></p><p>- Strong background in processor coherency and MP programming<br/><br/></p><p>- Project ownership throughout the project lifecycleDemonstrated team leadership experience with outstanding communication skillsHighly motivated self-starter with strong execution mindset and collaborative approach<br/><br/></p><p>- Post-silicon debug experience strongly preferred</p><br/></p> (ref:hirist.tech)