Principal Design Engineer

Job description

At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology.


Qualification : BE/ Btech or ME/M.Tech with 10+ Years of Experience

Location:

Position is based in Bangalore.


Job Description:

We are looking for strong technical team lead for IP Integration, subsystem creation, and QA for our SSG IP Integration and QA engineering team.

The role would include working with existing RTL, integration of PHYs and controllers to create sub-systems, and addition of new features.

In addition, responsibilities include ensuring various customer configurations are clean as part of verification regressions, and ensuring design is clean for all QA aspects in both Front End and Back End (these includes items like being Timing/LINT/RDC/CDC clean, consistency checks for all IP views etc.

A critical part of this role is for the technical lead to also oversee the adoption and roll out of Agentic AI initiatives into all aspects of IP Integration and QA including multi-agent connections in CDNS EDA flows.

They will work closely with various RnD IP leaders and Central Engineering teams around the world to ensure integration and release of IPs are handled on time and with Quality.

The lead should also be able to identify constant process improvement and automation to increase the efficiency of the entire RnD IP release process.

The role will include people management, and the lead would be responsible for technical and personal growth of their team.

This is a highly visible role as it is serves as a critical final touchpoint from RnD to Customers and our IP teams success hinges on the efficiency and throughput of this team.


Requirements:

+ Education:

+ College education in Electronics Engineering or Computer Engineering


+ Experience/Abilities:

+ Candidate should be proficient in ASIC development flows like RTL design flow steps like RTL coding, Simulation, compilation/testbench validation, Synthesis, Timing, DFT, lint, CDC, LEC etc.

+ Familiarity with Power Flow (UPF/CPF).

+ Experience with functional simulation using Verilog/System Verilog and ability to debug existing Verilog/System Verilog test cases with little or no help from the designer

+ Good in Scripting languages(Shell, Perl, TCL, Python) and automation of design database qualification and packaging.

Checks and validation of package consistency.

+ Bug reporting and resolution closure with IP providers

+ Ability to debug synthesis/timing analysis constraints, reports, logs

+ Ability to learn new tools/flows and develop methodology if needed.


+ Soft Skills:

+ Ability to build and maintain close relationships with all stake holders such as RnD, Application/Product Engineers, Program Managers, Sales, etc

+ Strong communication skills, both oral and written

+ Need to be results and data driven while being able to pay attention to details

+ Good time management skills to balance multiple high-priority projects.

+ Ability to efficiently lead and train teams

+ Fastidious approach to building automated processes.

+ Strong interpersonal and relationship-building skills.

+ Passionate about quality and ensuring our customer have the best experience


+ Additional Desirable Qualifications:

+ Familiarity with SerDes/DDR/other Design-IP’s & Analog design flows

+ Familiarity with IP release and tracking management systems


We’re doing work that matters.

Help us solve what others can’t.



Additional Jobs (https://cadence.wd1.myworkdayjobs.com/addl_jobs)


Equal Employment Opportunity Policy:

Cadence is committed to equal employment opportunity throughout all levels of the organization.

+ Read the policy(opens in a new tab) (https://www.cadence.com/content/dam/cadence-www/global/en_US/documents/company/careers/equal-employment-opportunity-policy.pdf)

We welcome your interest in the company and want to make sure our job site is accessible to all.

If you experience difficulty using this site or to request a reasonable accommodation, please contact staffing@cadence.com.


Privacy Policy:

Job Applicant If you are a job seeker creating a profile using our careers website, please see the privacy policy(opens in a new tab) (https://www.cadence.com/en_US/home/privacy/privacy-policy.html) .



E-Verify Cadence participates in the

E-Verify program in certain U.S. locations as required by law.

Download More Information on E-Verify (64K) (https://www.cadence.com/content/dam/cadence-www/global/en_US/documents/company/careers/e-verify-participation-poster.pdf)


Cadence plays a critical role in creating the technologies that modern life depends on.

We are a global electronic design automation company, providing software, hardware, and intellectual property to design advanced semiconductor chips that enable our customers create revolutionary products and experiences.


Thanks to the outstanding caliber of the Cadence team and the empowering culture that we have cultivated for over 25 years, Cadence continues to be recognized by Fortune Magazine as one of the 100 Best Companies to Work For.


 Our shared passion for solving the world’s toughest technical challenges, our dedication to pushing the limits of the industry, and our drive to do meaningful work differentiates the people of Cadence.



Cadence is proud to be an equal opportunity employer.

All qualified applicants will receive consideration for employment without regard to race, color, sex, age, national origin, religion, sexual orientation, gender identity, status as a veteran, basis of disability, or any other protected class.



Cadence is committed to creating a diverse environment and is proud to be an equal opportunity employer.

All qualified applicants will receive consideration for employment without regard to race, color, sex, age, national origin, religion, sexual orientation, gender identity, status as a veteran, basis of disability, or any other protected class.

Required Skill Profession

Other General