Principal soc design verification methodology engineer

Principal Gen AI based So C Design Verification Methodology EngineerWe are a US based Stealth mode Start-uplocation: Hyderabad / Bangalore / Remote ( any where in India )We unify the processes used in Semiconductor and Hardware Systems design - thus reducing bugs, improving efficiency and productivityOur breakthrough technology has drawn investment from Silicon Valley’s boldest VCs and semiconductor pioneers.

Beyond capital, they bring decades of expertise and powerful networks,Senior Application Engineer, AI based CAD systemsThis role offers an exceptional opportunity to lead product definition, validation and customer engagement.Key Responsibilities:Work with the software development team to define the detailed feature requirementsCreate and execute validation plans for the featuresWork with multi-functional and distributed team to drive issues and features to closureDevelop end-to-end flows on sample designs/scenarios and collaterals/demosWho you are:BS/MS in Electronics or equivalent10-12+ years of working experience in So C DV or IP design for high speed interfacesProven experience in working with System Verilog/UVM/IP Exact/System RDLExperience in defining hardware design/verification plansGit, CI/CD, Linux Scripting, Tcl, PythonContact:UdayMulya 'Mining The Knowledge Community'