<p><p><b>JD : </b> Sr RTL Engineer <br/><br/><b>Experience : </b> 5-20 Years<br/><br/><b>Mode : </b> Full Time with Our Client<br/><br/><b>Location : </b> Kochi & Thiruvananthapuram , Bangalore, Pune, Chennai, Hyderabad, Ahmedabad <br/><br/><b>NP : </b> Immediate-90days<br/><br/> Senior ASIC/SoC RTL Engineer/Lead <br/><br/><b>Role : </b> ASIC RTL Engineer / Digital Design<br/><br/><b>Mandatory Skill : </b> <br/><br/></p><p>- RTL, Coding, Design, IP Design, SOC Development, Lint, CDC , Micro Architecture - Mandatory <br/><br/></p><p>- PCIe/DDR/Ethernet - Any One<br/><br/></p><p>- I2C,UART/SPI - Any One <br/><br/></p><p>- Spyglass Lint/CDC / Synopsys DC / Verdi/Xcellium - Any One<br/><br/></p><p>- Scripting languages like Make flow, Perl ,shell, python - Any One<br/><br/><b>Good to have : </b> <br/><br/></p><p>- Processor architecture / ARM debug architecture<br/><br/></p><p>- Debug issues for multiple subsystems<br/><br/></p><p>- Create/review design documents for multiple subsystems<br/><br/></p><p>- Able to support physical design, verification, DFT and SW teams on design queries and reviews<br/><br/><b>Details JD : </b> <br/><br/></p><p>- Expertise in SoC subsystem/IP design <br/><br/></p><p>- Expertise in IP design, Subsystem/Cluster and SoC level integration using Verilog/System Verilog <br/><br/></p><p>- In depth knowledge on RTL quality checks (Lint, CDC) <br/><br/></p><p>- Knowledge of synthesis and low power is a plus <br/><br/></p><p>- Good understanding of AMBA bus protocols (AXI, AHB, ATB, APB) <br/><br/></p><p>- Good understanding of timing concepts <br/><br/></p><p>- Knowledge of one or more of the interface protocols :<br/><br/></p><p>a.
PCIe <br/><br/></p><p>b.
DDR <br/><br/></p><p>c.
Ethernet <br/><br/></p><p>d.
I2C, UART, SPI <br/><br/></p><p>- Expertise in setting up and using tools like :<br/><br/></p><p>a.
Spyglass Lint/CDC <br/><br/></p><p>b.
Synopsys DC <br/><br/></p><p>c.
Verdi/Xcellium <br/><br/></p><p>- Understanding of scripting languages like Make flow, Perl ,shell, python etc <br/><br/></p><p>- Understanding of processor architecture and/or ARM debug architecture is a plus <br/><br/></p><p>- Able to help and debug issues for multiple subsystems <br/><br/></p><p>- Able to create/review design documents for multiple subsystems <br/><br/></p><p>- Able to support physical design, verification, DFT and SW teams on design queries and reviews<br/></p><br/></p> (ref:hirist.tech)