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Urgent! RTL - Tech Lead Job Opening In Bengaluru – Now Hiring CoreEL Technologies



Job description

RTL -Tech Lead.

Experience: 7 to 9 years’ experience.

Educational Qualification: Engineering degree in E&C

Location: Bangalore

Job Description:

  • Define DSP, System and Board architecture.
  • Create proposal for new project enquiries
  • Experience in handling the team.
  • Partition the algorithms for implementing in FPGA and/or in SW.

    Identify the building blocks & Signal Processing functions.
  • Provide estimates on FPGA resources, computation bandwidth, and memory bandwidth.
  • Create module level details from architecture, coding, simulation and perform peer reviews.
  • Define, create and maintain all project related documentation, especially design documents with detailed analysis reports.

    Provide support to customer during integration phases at test sites and support to production teams
  • Creating SRS, ATP for the system
  • Apply the methodologies for design, verification or validation
  • Provide support to customer during integration phases at test sites
  • Defining the architecture of RTL functions, partitioning algorithms
  • HDL Coding, review
  • Simulation and Implementation
  • Testing on board and debugging
  • Project ownership including identifying risks, dependencies, tracking project schedule, discussions with customers, design reviews.
  • Supervise and mentor at least 2 to 3 DE/SDEs
  • Team Management
  • Professional Skills:

    · Proficiency in VHDL · Xilinx tools for synthesis and implementation

    · Thorough understanding of Xilinx FPGA’s

    · Functional and Timing Simulation

    · Hardware Design : Logic Design & Debugging expertise

    · FPGA Design : VHDL/Verilog RTL Coding, System C/ System Verilog

    · FPGA Design : FPGA Synthesis & PAR Tools

    · Fluency, good communication & presentation skills.

    · Configuration/Version control tools like SVN.

    · Knowledge on sRIO, PCIe, Ethernet and other protocols.

    Desired Skill Set:

    · Implementing DSP algorithms in FPGA environment for Radar and Electronic Warfare systems.

    · Interact with SW and HW teams to define the architecture/system partitioning

    · FPGA development flow: micro-architecting, RTL coding, Synthesis & implementation flow, verification and validation.

    · Modeling the algorithms in Octave/MATLAB, generating test

    vectors, visualizing data.

    · Converting floating point modules to FPGA friendly fixed point modules.

    · Familiarity with DSP Xilinx IP cores and customization options : FFT, FIR, DDC, NCO etc., · Thorough knowledge on interfacing with ADCs and DACs and interpreting their performance.

    · Transferring data from FPGA over sRIO, PCIe, Ethernet and other protocols.

    · Configuration/Version control tools like SVN


    Required Skill Profession

    Computer Occupations



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