Requirement:-
Reports to: Manager / Senior Manager - FPGA
Experience: 3-10 Years
Roles and Responsibilities:
You will be engaged in end-to-end system development involving complex modules - related to carrier-grade optical transmission / Ethernet switch/aggregation/wireless product development.
You will work very closely with Product-Line Management team, Product Verification team to understand the customer requirement to incorporate innovativeness and value-additions to product development.
You will refer standards, plan and execute the module level design and verification.
You will also work closely with HW & SW architects to understand and influence the module level design/architecture and implement the design changes in Verilog or SV. You will validate the design and work closely with other teams / members still the product verification cycle.
Skills:
Strong digital design concepts RTL front end design experience in Verilog and/or VHDL and/or SV is must Good understanding of FPGA architecture of leading vendors is must Experience in micro-architecture design/development is must Experience in Static timing analysis, timing constrains, clock-domain crossing is must Hands-on experience with EDA tools on timing closure is must Experience in verification/simulation tools is must Experience in either OTN (ITU-T G.709) or Ethernet (802.3) or SONET/SDH is must Knowledge of scripting languages Perl, Python, TCL is preferred Knowledge of version control systems like svn/cvs is preferred Experience with FPGA test automation / regression is preferred Familiarity with encryption / authentication algorithms or protocols is preferred Good documentation and communication skills Evaluate and make decisions around the use of new or existing technologies and tools Ability to guide /mentor junior members of team