Hi All,
Eximietas Hiring Senior Synthesis/Constraints.
Experience: 10+ Years.
Location: Bengaluru or Visakhapatnam or San Jose, Bay Area, & Austin, USA.
Anyone with a Valid H1B or Already in US.
Block / Subsystem / Partition / Full chip.
- Role: Synthesis and Timing Constraint Engineer.
- EDA Tool: Cadence Genus & Fishtail.
- Node: TSMC 3nm / 5nm.
- UPF Implementation hands-on is must.
- Synthesis PPA optimization, Hierarchical partition synthesis, Lint, Sanity Checks.
- Timing constraints generation and validation.
- Tcl, Perl, Python Scripting mandatory.
Interested Candidates please start sharing your resumes: maruthiprasad.e@eximietas.design