<p></p><p><b>Job Description :</b><br/><br/><b>Key Responsibilities :</b><br/><br/></p><p>- Block-level and sub-system DFT micro-architecture including SCAN, MBIST, IP tests, JTAG<br/><br/></p><p>- Develop and execute test insertion flow for scan, MBIST, JTAG<br/><br/></p><p>- Estimate and achieve targeted test coverage.<br/><br/></p><p>- Run RTL and gate-level simulation for all DFT modes.<br/><br/></p><p>- Develop and debug timing constraints for all DFT modes.<br/><br/></p><p>- Verify test patterns pre-silicon and post-silicon<br/><br/></p><p>- Write scripts in TCL and Perl to achieve productivity enhancements through automation.<br/><br/><b>Required Background :</b><br/><br/></p><p>- In-depth knowledge of VLSI design as well as hardware description languages such as Verilog.<br/><br/></p><p>- Experience with complex block-level and SOC-level DFT execution in advanced finFET technology.<br/><br/></p><p>- Deep knowledge with EDA tools such as Synopsys Tetramax or Mentor Tessent.<br/><br/></p><p>- Good problem solving and debug capabilities is a preferred plus.<br/><br/></p><p>- Good knowledge of hardware simulation tools like VCS, Verdi, etc.<br/><br/></p><p>- Proficient in scripting languages Should be proficient at working with cross functional and cross site teams.<br/><br/></p><p>- Must possess good communication skills, be a self-driven individual and a good team player.<br/><br/><b>Personal Attributes :</b><br/><br/></p><p>- Can-do attitude.
</p><p><br/></p><p>- Strong team player.
</p><p><br/></p><p>- Curious, creative, and good at solving problems.
</p><p><br/></p><p>- Execution and results oriented.
Self-driven, Thinks Big and is highly accountable.
</p><p><br/></p><p>- Good communication skills.</p><br/><p></p> (ref:hirist.tech)