SoC Design Lead – HBM & LPDDR Memory Controllers
Bangalore / Hyderabad
Job Title: SoC Design Lead – HBM & LPDDR Memory Controllers
We are a well-funded early-stage startup building the next generation of high-performance SoC design technologies.
We’re seeking a seasoned SoC Design Lead with expertise in memory controller microarchitecture and RTL development to drive the design of one of HBM or LPDDR controller IP.
This is a unique opportunity to shape our technology portfolio in advanced memory systems, while working hands-on to deliver industry-leading solutions for AI, HPC, and next-gen SoCs.
Responsibilities
- Lead the design and development of high-performance memory controllers for HBM (HBM2/2E/3) or LPDDR (LPDDR4x/5/5x).
- Own the microarchitecture definition, from early exploration and research to detailed architectural specifications.
- Develop and optimize RTL code to meet aggressive performance, power, and area targets.
- Collaborate with verification teams on test plans, coverage, debug, and formal assertions to ensure robust validation.
- Work with PHY teams to define and validate DFI-compliant interfaces, training flows, calibration, and timing closure.
- Partner with system architects and firmware/software teams to define performance requirements, configuration flows, and integration strategies.
- Drive quality-of-service (QoS), scheduling, and re-ordering logic to maximize memory bandwidth and efficiency.
- Provide technical leadership and mentorship, establishing best practices in microarchitecture, RTL design, and methodology.
Qualifications & Preferred Skills
- BS/MS in Electrical Engineering, Computer Engineering, or Computer Science.
- 12–15 years of hands-on experience in microarchitecture and RTL development of
- Memory Controller subsystems.
- Proven track record designing high-performance memory controllers (HBM, LPDDR, DDR).
- Strong expertise in JEDEC memory standards: JESD235 (HBM2/3), JESD209 (LPDDR4x/5).
- Familiarity with DFI interface specifications and experience integrating with memory PHY IP.
- Proficiency in Verilog, SystemVerilog, and strong understanding of digital design fundamentals (timing, low power, multi-clock domains).
- Experience with QoS, re-ordering, refresh scheduling, and low-power modes in memory controllers.
- Knowledge of PHY-level training flows (e.g., write leveling, read training, calibration) is highly desirable.
- Familiarity with industry-standard EDA tools and design flows.
- Knowledge of Python or other scripting/programming languages for automation is a plus.
- Excellent problem-solving skills and attention to detail, with the ability to work across the full design lifecycle.
- Strong communication and leadership skills, comfortable working in a fast-paced startup environment.
Contact:
Uday
Mulya Technologies
Mining The Knowledge Community