Job Overview
            
                
                    Company
                    Mulya Technologies
                 
                
                
                    Category
                    Computer Occupations
                 
                
             
            
            
         
        
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            Job Description
            
                Job Title: SoC Design Lead – High-Speed I/O Controller IP
Bangalore / Hyderabad
We are a well-funded early-stage startup building the next generation of high-performance SoC design technologies.
We’re looking for a seasoned SoC Design Lead with deep expertise in microarchitecture and RTL development to drive the design of one of PCIe, CXL, or UCIe controller IP.
This is a unique opportunity to shape both our technology roadmap and engineering culture, while working hands-on at the cutting edge of high-speed I/O innovation.
Responsibilities
Own the microarchitecture for high-speed I/O controllers (PCIe, CXL, UCIe) – from concept to production-ready RTL.
Lead architectural exploration, research, and specification development, balancing performance, power, and area trade-offs.
Write and optimize RTL code in Verilog/SystemVerilog, ensuring robust, scalable designs.
Partner with verification teams to define assertions, test plans, and debug flows, driving high-quality coverage and sign-off.
Collaborate with physical design engineers on implementation, timing closure, and silicon validation.
Work closely with software/firmware teams to define configuration, integration, and performance requirements.
Provide technical leadership and mentorship within the design team, fostering best practices in architecture, coding, and methodology.
Qualifications & Preferred Skills
BS/MS in Electrical Engineering, Computer Engineering, or Computer Science.
12–15 years of hands-on experience in microarchitecture and RTL design.
Proven track record in large-scale, high-speed, pipelined, and low-power digital designs.
Deep understanding of at least one high-speed I/O protocol (PCIe, CXL, or UCIe); multi-protocol experience is a strong plus.
Proficiency in Verilog, SystemVerilog, and familiarity with industry-standard EDA tools and flows.
Experience developing IP blocks for high-speed I/O controllers; knowledge of PHY integration is a plus.
Strong problem-solving and debug skills; ability to work across the full chip development lifecycle.
Familiarity with Python or other modern scripting/programming languages for automation and productivity is a plus.
Excellent communication skills and a collaborative mindset, with experience working in cross-functional teams.
Self-starter comfortable in a fast-paced startup environment, with the ability to balance leadership and hands-on contributions.
Contact:
Uday
Mulya Technologies
muday_bhaskar@yahoo.com
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