Urgent! Softpath Technologies - DFT Verification Engineer - Embedded System Job Opening In Bengaluru – Now Hiring Softpath Technologies LLC
<p><p><b>Job Title : </b> DFT Verification Engineer - DDR IP/Subsystem Focus<br/><br/><b>Experience : </b> 4 - 9 Years<br/><br/><b>Location : </b> Bangalore (Only Local Candidates Preferred)<br/><br/><b>About the Role : </b><br/><br/>We are seeking a talented and motivated DFT (Design for Test) Verification Engineer with solid hands-on experience in DDR IP or Subsystem-level verification.
The ideal candidate should have strong expertise in DFT pattern generation and gate-level simulations, particularly targeting DDR interfaces and working with JTAG-based test infrastructure.<br/><br/>You will be responsible for generating silicon test patterns, validating them through simulations, and ensuring robust testability for high-speed DDR interfaces.
This role involves close collaboration with RTL designers, DFT architects, and validation engineers to deliver high-quality test solutions for production silicon.<br/><br/>This is a critical engineering position for someone passionate about silicon test strategy, DDR technologies, and pre-silicon verification in advanced SoC designs.<br/><br/><b>Key Responsibilities : </b><br/><br/>- Work as part of the DFT team to verify DDR IP/subsystems using pattern-based testing methodologies.<br/><br/>- Generate and validate JTAG-based test patterns specifically for DDR interfaces using industry-standard tools and flows.<br/><br/>- Perform Gate-Level Simulations (GLS) to validate generated test patterns and ensure correct functionality in the post-synthesis/post-layout netlists.<br/><br/>- Develop verification plans, write testbenches, and debug test pattern failures across RTL and gate-level simulations.<br/><br/>- Interface with RTL, validation, and test teams to ensure seamless test integration and silicon readiness.<br/><br/>- Contribute to ATPG/MBIST pattern integration and test coverage improvements for DDR-related logic.<br/><br/>- Ensure patterns meet structural and functional test goals without impacting design performance.<br/><br/>- Review timing reports and ensure pattern compliance with design timing requirements.<br/><br/>- Collaborate closely with DFT architects to enhance test insertion methodologies for high-speed interfaces like DDR.<br/><br/>- Support lab bring-up/debug of test patterns on silicon (if required).<br/><br/>- Automate test pattern generation, result analysis, and validation flows using scripting (Tcl, Perl, Python, etc.).<br/><br/><b>Required Skills and Qualifications : </b><br/><br/>- B.E./B.Tech or M.E./M.Tech in Electronics, Electrical, or VLSI Design.<br/><br/>- 4 to 9 years of industry experience in DFT Verification, with specific focus on DDR IP or DDR subsystem-level testing.<br/><br/>- Strong knowledge of DFT concepts including JTAG, boundary scan, scan insertion, ATPG, and MBIST.<br/><br/>- Proven experience in pattern generation and gate-level simulation for high-speed interfaces (DDR3/DDR4/LPDDR4/DDR5).<br/><br/>- Solid understanding of digital logic design, SoC architecture, and memory controller interfaces.<br/><br/>- Hands-on experience with Verilog/VHDL, SystemVerilog for testbenches, and simulation tools like VCS, NC-Sim, or Questa.<br/><br/>- Familiarity with DFT tools like TetraMAX, TestMAX, Tessent, or equivalent.<br/><br/>- Experience in post-synthesis/post-layout simulations, including STA timing reviews and glitch analysis.<br/><br/>- Proficient in scripting languages : Tcl, Perl, Python, or Shell.<br/><br/>- Strong debugging skills and ability to root-cause test failures across RTL and GLS domains.<br/><br/>- Excellent communication and teamwork skills; ability to work independently and within a fast-paced team.<br/><br/><b>Preferred Qualifications : </b><br/><br/>- Experience with low-power testing and UPF-based flows.<br/><br/>- Knowledge of SoC-level DFT integration, including hierarchical scan and clock domain crossings.<br/><br/>- Familiarity with lab environments and post-silicon validation.<br/><br/>- Understanding of DDR protocol standards and compliance requirements.<br/><br/><b>Why Join Us?</b><br/><br/>- Work on cutting-edge DDR memory subsystem validation in next-gen SoC designs.<br/><br/>- Be part of an experienced, collaborative, and technically focused team.<br/><br/>- Opportunity to impact DFT sign-off and first-silicon success of complex chips.<br/><br/>- Competitive compensation and career advancement opportunities.</p><br/></p> (ref:hirist.tech)
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Unlock Your Softpath Technologies Potential: Insight & Career Growth Guide
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