<p><p><b>Job Title :</b> STA Lead Full-Chip Static Timing Analysis<br/><br/><b>Experience Required :</b> 8+ Years<br/><br/><b>Location :</b> Bangalore, India<br/><br/><b>Job Mode :</b> Work From Office (WFO)<br/><br/><b>Industry :</b> Semiconductors / VLSI / ASIC the Role :</b></p><p><br/></p><p>We are looking for a highly skilled and experienced STA Lead Engineer to join our SoC/ASIC design team in Bangalore.
As an STA Lead, you will be responsible for driving timing closure and sign-off at the full-chip level, working with cross-functional teams to ensure first-time-right silicon.</p><br/>This role demands expertise in Static Timing Analysis (STA) at both block and top levels, deep knowledge of multi-mode/multi-corner (MMMC) analysis, and experience working with advanced technology nodes (7nm, 5nm, and below).
You will take complete ownership of full-chip timing constraints, analysis, ECO closure, and sign-off processes.<br/><br/>This is a key leadership position, suitable for someone who thrives in a fast-paced, high-complexity semiconductor environment and enjoys solving deep technical challenges while collaborating with a world-class engineering team.</p><p><b><br/></b></p><p><b>Key Responsibilities :</b><br/><br/></p><p>- Lead full-chip static timing analysis across multiple modes and PVT (Process-Voltage-Temperature) corners.<br/><br/></p><p>- Take full ownership of top-level SDC (Synopsys Design Constraints) generation, validation, and continuous refinement.<br/><br/></p><p>- Collaborate closely with block-level STA, synthesis, physical design, DFT, and clock architecture teams to drive convergence and timing closure.<br/><br/></p><p>- Identify and resolve timing violations (setup/hold) using engineering change orders (ECOs), floorplan improvements, and clock optimization strategies.<br/><br/></p><p>- Perform MMMC timing analysis covering OCV, AOCV, and POCV variations to ensure robust and accurate results.<br/><br/></p><p>- Integrate STA reports from various blocks and carry out hierarchical full-chip STA and timing sign-off.<br/><br/></p><p>- Partner with DFT engineers to analyze and fix scan shift timing, capture timing, and at-speed test paths.<br/><br/></p><p>- Develop and maintain automation scripts in Tcl, Perl, or Python for report generation, violation tracking, and metrics dashboards.<br/><br/></p><p>- Define and communicate timing budgets and constraints to IP/block owners and ensure adherence throughout the design cycle.<br/><br/></p><p>- Work with EDA vendors and foundries to address tool issues, model inaccuracies, and sign-off guideline updates.<br/><br/></p><p>- Maintain documentation, best practices, and templates for STA methodology across Skills and Qualifications :</b></p><p><br/></p>- Bachelors or Masters degree in Electronics, Electrical, or Computer Engineering.<br/><br/></p><p>- 8+ years of hands-on experience in Static Timing Analysis with a focus on full-chip timing convergence.<br/><br/></p><p>- Strong working knowledge of Synopsys PrimeTime, SDC, and timing ECO flows.<br/><br/></p><p>- Proven expertise in hierarchical STA, MMMC analysis, and variation-aware timing closure (OCV/AOCV/POCV).<br/><br/></p><p>- Solid understanding of digital design principles, clock tree architecture, floorplanning, and DFT timing.<br/><br/></p><p>- Proficiency in scripting languages like Tcl, Perl, and Python.<br/><br/></p><p>- Experience with advanced technology nodes (7nm, 5nm or lower) and familiarity with foundry constraints and sign-off requirements.<br/><br/></p><p>- Strong analytical and problem-solving skills with a detail-oriented approach to debugging complex issues.<br/><br/></p><p>- Excellent communication skills and the ability to coordinate across cross-functional global Qualifications :</b></p><p><br/></p>- Exposure to multi-die or chiplet-based SoC integration is a strong plus.<br/><br/></p><p>- Prior experience in leading a team of STA engineers or mentoring junior members.<br/><br/></p><p>- Familiarity with static IR drop, crosstalk, and noise-aware STA.<br/><br/></p><p>- Understanding of low-power techniques (UPF/CPF-based flows).
</p><p><b><br/></b></p><p><p><b>Why Join Us ?</b></p><p><br/></p>- Work on next-generation SoC designs at the forefront of semiconductor technology.<br/><br/></p><p>- Collaborate with industry-leading engineers across synthesis, P&R, DFT, and verification teams.<br/><br/></p><p>- Be part of a high-impact, technically focused team where your contributions matter.<br/><br/></p><p>- Competitive compensation, benefits, and career growth opportunities.</p><br/></p> (ref:hirist.tech)