Job Overview
Company
MaimsD Technology
Category
Computer Occupations
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Job Description
<p><p><b>Description :</b><br/><br/>Job Title : STA Engineer<br/><br/>Location : Bangalore, India<br/><br/>Experience : 4+ years<br/><br/><b>Job Overview :</b><br/><br/>We are seeking a highly skilled Design Verification and Static Timing Analysis (STA) Engineer with expertise in scan, ATPG, and SV UVM methodologies, as well as pre- and post-layout STA.
</p><p><br/></p><p>The ideal candidate will be responsible for ensuring the timing closure of complex SoCs, integrating IP-level constraints, and developing custom scripts for timing fixes.<br/><br/><b>Key Responsibilities :</b><br/><br/><b>Scan & ATPG :</b><br/><br/>- End-to-end experience in scan chain insertion, ATPG pattern generation, and post-silicon validation.<br/><br/>- Collaborate with design and verification teams to ensure full coverage and fault-free designs.<br/><br/><b>SV UVM Verification :</b><br/><br/>- Develop and maintain SV UVM testbenches for functional verification of IPs and SoCs.<br/><br/>- Create reusable verification components, sequences, and monitors to validate design functionality.<br/><br/>- Work closely with design engineers to debug functional issues and ensure compliance with specifications.<br/><br/><b>STA & Timing Closure :</b><br/><br/>- Develop pre-layout and post-layout constraints to achieve timing closure at full-chip level.<br/><br/>- Integrate IP-level constraints into the full-chip STA methodology.<br/><br/>- Perform DMSA (Design Margin Static Analysis) and implement timing fixes using custom scripts.<br/><br/><b>Technical Skills :</b><br/><br/>- Strong hands-on experience in scan and ATPG methodologies.<br/><br/>- Proficiency in SV UVM for functional verification.<br/><br/>- STA tool expertise and constraint development experience.<br/><br/>- Scripting experience (Perl, TCL, Python) for automation and timing fixes.<br/><br/><b>Qualifications :</b><br/><br/>- Bachelors or Masters degree in Electronics, VLSI, or related field.<br/><br/>- Minimum 4 years of experience in VLSI design verification, SV UVM, or STA.<br/><br/>- Strong problem-solving skills and ability to work independently and in teams.<br/><br/><b>Why Join Us :</b><br/><br/>- Opportunity to work on cutting-edge SoC designs.<br/><br/>- Collaborative environment with experienced VLSI engineers.<br/><br/>- Career growth and exposure to advanced design verification and timing methodologies.</p><br/></p> (ref:hirist.tech)
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