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Synthesis and Static Timing Analysis - Staff Design Engineer/Design Manager Job Opening In Bengaluru – Now Hiring Eteros Technologies

Synthesis and Static Timing Analysis Staff Design Engineer/Design Manager

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Job description

Company: Eteros Technologies India Private Limited
Eteros Technologies, Inc.

is a Semiconductor Engineering services startup, head quartered in the heart of the Silicon Valley, San Jose, CA, USA.

Eteros Technologies India Pvt Ltd is a wholly owned subsidiary offices in Bangalore, Noida, Hyderabad and Ahmedabad
• Our world-wide customers are amongst The Who's who in the semiconductor industry.

Eteros works not only with some of the top 20 semiconductor startups in the world but boasts of customers who are among the most respected publicly traded semiconductor companies.
• Eteros engineers work on cutting edge technology nodes while working on the state-of-the art designs in the AI/ML, Datacenter, Automotive and 5G domains.

Eteros engineers work with some of the brightest, innovative and successful engineers and leaders around the world.

A one-of-a-kind opportunity where young Eteros engineers showcase their ability and experience world-wide from day 1 while learning from some of the world's most well-respected companies.
• We are not your traditional design services company offering staff augmentation.

Eteros engineers are treated as an integral part of the customer team and routinely are responsible for turnkey, end-to-end ownership and delivery, whether it is Implementation, Digital and Mixed Signal Verification, DFT or Analog Design and Layout.

Eteros and our engineers work closely with our customers to define and set methodologies and design flows.
• Eteros invests in our engineers.

Our engineers are continuously learning, on and off the job.

They are able to grow the breadth and depth of knowledge.

We believe in preparing our employees for the fast-track in career development as well as longevity
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Job Title/Role: Synthesis and Static Timing Analysis - Staff Design Engineer/Design Manager
Location : Bangalore/Hyderabad/Ahmedabad/Noida
Experience Level : 6+ Years
Industry : Semiconductors
Employment Type : Full-time
Job Functions : Engineering
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Summary
Join a development team and lead the synthesis, static timing and DFT efforts for an advanced mixed signal chip for a high-profile Silicon Valley startup.
In this highly visible role, as part of a highly talented team you will be at the heart of the Soc design effort interfacing with all disciplines with critical impact in getting functional products to of customers quickly.

As a Sr, ASIC STA Engineer, you will be a part of the SOC digital design team responsible for providing integrated solutions into a growth industry
Key Qualifications
The position requires thorough knowledge of the ASIC design timing closure flow and methodology.
• BTech/MTech/PhD with at least 6+ years hands-on experience in ASIC timing constraints generation and timing closure.
• Expertise in STA tools (Tempus and Primetime) and methodologies for timing closure with a good understanding of OCV, noise and crosstalk effects on timing.
• Familiarity with all aspects of timing closure of high-performance, mixed-signal SoCs in advanced finFET technology nodes, preferably 7nm.
• Knowledge of timing corners/modes and process variations.
• Knowledge of low-power techniques including clock gating, power gating and millivoltage designs.

Proficient in scripting languages (Tcl and Perl).
• ECO timing flow
• Strong communication skills are a pre-requisite as the candidate will interface with a lot of different groups (e.g. digital design, verification, DFT, physical design, etc.).
• Familiarity with RTL, synthesis, logic equivalence, DFT, floor-planning, and backend related methodology and tools.
• Must be able to solve complex problems and independently drive tasks to completion in a timely manner.
• Be able to work under limited supervision and take complete accountability.
Responsibilities Include
• Full chip and block level timing closure ownership throughout the entire project cycle (RTL, synthesis, and physical implementation).
• Develop and maintain methodology and flows related to timing verification and closure.
• Generation of block and full chip timing constraints.
• Analyze timing reports and utilize scripting techniques to develop insights and drive rapid Eteros Technologies, Inc.

Confidential Sep 2020 timing closure.
• Support digital chip integration work and flows
What's in it for you
• Work on leading edge technologies
• An opportunity for career development and growth
• Competitive compensation
• Medical Benefits and more

Required Skill Profession

Engineers


  • Job Details

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