System Verification Engineer - System Verilog

<p>his is what you are responsible for :<br/><br/>- Develop and maintain verification plans, testbenches, and test cases for ASIC designs.<br/><br/>- Collaborate with design and architecture teams to understand design specifications and requirements.<br/><br/>- Design and implement System Verilog/UVM-based verification environments.<br/><br/>- Create and execute test cases to verify functionality, performance, and compliance with specifications.<br/><br/>- Debug failures and drive issues to closure, working closely with cross-functional teams.<br/><br/>- Mentor junior team members and provide technical guidance.<br/><br/>- Contribute to the continuous improvement of verification methodologies and best practices.<br/><br/>- Create and maintain verification environments for SOCs.<br/><br/>Necessary Qualifications :<br/><br/>- 8 years of experience in ASIC verification, preferably in a senior or lead role.<br/><br/>- Strong expertise in SystemVerilog, UVM, OOP concepts and verification methodologies.<br/><br/>- Experience with verification tools such as VCS, QuestaSim, or similar.<br/><br/>- Proven track record of successfully delivering complex ASIC verification projects.<br/><br/>- Excellent problem-solving and debugging skills.<br/><br/>- Strong communication and teamwork abilities.<br/><br/>Preferred Qualifications :<br/><br/>- Experience with scripting languages such as Python or Perl.<br/><br/>- Knowledge of industry standards and protocols (e.g., PCIe, DDR, USB, Ethernet).<br/><br/>- Knowledge on the on chip interconnects, memory and processor subsystems.<br/><br/>- Familiarity with formal verification techniques.<br/><br/></p> (ref:hirist.tech)