We need experienced engineers to verify an IP/full-chip using System Verilog/UVM.
Expertise in PCIe/DDR verification is preferable at IP/chip level.
Skills:
- Overall 3+ years industry experience in Design Verification using System-Verilog/C/UVM.
- Generic knowhow on Digital Design and Verification methodologies.
- Experience in System Verilog/UVM based IP/SoC verification using advanced technologies.
- Good understanding of Constraint based Random verification;
VIP coding;
Test Plan design;
Test cases coding;
Coverage strategies and measurement - Proficient in EDA tools used for Design Verification (e.G. Cadence/Mentor/Synopsys simulation suites;
Verilator). - Working knowledge of Unix, Linux and SKILL, Shell/Python Script ability.
- Quick learner with excellent interpersonal, verbal/written communications, problem solving and decision-making skills
Traits:
- Adaptable, Flexible, Global Approach/Synthesis, creative and capable of working independently as well as a team player.
Should have a strong sense of urgency. - Solutions orientation;
Quality driven;
Execution minded