Tenstorrent - CPU Core Feature Verification & Debug Engineer

<p><p><b>Description : </b><br/><br/>Principal/Senior CPU Core Feature Verification and Debug Engineer<br/><br/><b>Location : </b> Bangalore, India<br/><br/><b>Experience : </b> 410 years<br/><br/><b>About the Role : </b><br/><br/>Tenstorrent, a leader in cutting-edge AI technology and high-performance computing, is seeking a highly skilled CPU Core Feature Verification and Debug Engineer to join our team in Bangalore.

This role is crucial for verifying our custom, high-performance RISC-V CPU core from the ground up.

You will be responsible for both ISA (Instruction Set Architecture) and detailed microarchitectural verification at the core level, contributing significantly to a platform that unifies innovations across software, compilers, and semiconductors.

We are hiring contributors across all seniorities (415 years).<br/><br/><b>Key Responsibilities : </b><br/><br/>- Core Level Verification : Serve as the core-level feature/testplan verification engineer, responsible for comprehensive verification of the CPU ISA and microarchitectural features of the high-performance Out-of-Order (OOO) CPU.<br/><br/>- Stimulus Generation : Develop and integrate sophisticated UVM-based stimulus generation targeting both complex ISA compliance and specific microarchitectural scenarios.<br/><br/>- Debug and Analysis : Execute in-depth debugging of RTL (Register-Transfer Level) and Design Verification (DV) issues within a simulation environment, demonstrating proficiency in waveform and log file-based debug techniques.<br/><br/>- Test Development : Utilize assembly, C/C++ to develop targeted tests for feature verification and coverage closure.<br/><br/>- Verification Environments : Work proficiently across various verification environments, including simulation, formal verification, and emulation setups.<br/><br/>- Tooling and Scripting : Maintain hands-on proficiency with scripting languages (Python, PERL) for test automation, data processing, and workflow enhancement.<br/><br/>- Design & Simulators : Leverage knowledge of hardware description languages (Verilog, VHDL) and industry-standard simulators (VCS, NC, Verilator) for effective verification.<br/><br/><b>Required Skill Set (Mandatory Skills) : </b><br/><br/>- Experience : 410 years of relevant experience in CPU verification, design verification, or computer architecture.<br/><br/>- CPU Microarchitecture : Strong background and demonstrated experience with high-performance Out-of-Order (OOO) CPU microarchitecture.<br/><br/>- ISA Knowledge : Experience and strong understanding of one or more major ISAs : x86, ARM, or RISC-V.<br/><br/>- Debug Expertise : Proven expertise in debugging RTL and DV environments, with proficiency in waveform and log file analysis.<br/><br/>- Test Development : Experience using assembly, C/C++, and UVM for test stimulus generation.<br/><br/>- Technical Tools : Hands-on experience with scripting (Python, PERL) and simulators (VCS, NC, or Verilator).<br/><br/>- Fundamentals : Strong problem-solving and debug skills across various levels of design hierarchies.<br/><br/><b>Preferred Skills : </b><br/><br/>- Specific experience with the RISC-V ISA and its extensions.<br/><br/>- Prior experience working in an AI/accelerator domain.<br/><br/>- Familiarity with functional coverage closure and formal verification methodologies.<br/><br/>Principal/Senior CPU Core Feature Verification and Debug Engineer</p><br/></p> (ref:hirist.tech)