VLSI Design Engineer - System Verilog

<p><b>Mandatory : Looking for candidates who can join immediately or max in 15 days only apply.</b><br/><br/>Experience : 5 - 8 Years<br/><br/></p><p>Expertise in one or more of the following domains : </p><p><br/></p><p>- Power Optimization : Experience with low-power design techniques and methodologies, including the use of the Unified Power Format (UPF).<br/><br/>- Timing Optimization : Proficiency in static timing analysis (STA) and experience with design constraints using the Synopsys Design Constraints (SDC) format.<br/><br/>- Functional Safety Analysis : Deep understanding of functional safety concepts and standards (e.g., ISO 26262), and experience with related analysis techniques like FMEDA and FTA.<br/><br/>- Experience with industry-standard Electronic Design Automation (EDA) tools from vendors such as Synopsys, Cadence, or Siemens EDA.<br/><br/>- Proficiency in hardware description languages (HDLs) such as Verilog and SystemVerilog.<br/><br/>- Strong scripting skills in Python and Tcl for tool automation and flow development.<br/><br/>- Solid understanding of the chip design and implementation flows, from RTL to GDSII.<br/><br/>- Excellent problem-solving, debugging, and analytical skills.<br/><br/>- Strong communication and presentation skills, with the ability to explain complex technical concepts to both technical and non-technical audiences.<br/><br/>Requirements : </p><p><br/></p><p>Required Qualifications :</p><p><br/></p><p>- Bachelor's or Master's degree in Electrical Engineering, Computer Engineering, or a related field.<br/><br/>- 5+ years of hands-on experience in chip design, with a strong focus on RTL design, synthesis, static timing analysis (STA), or power integrity.</p> (ref:hirist.tech)