Title: STA/Synthesis EngineerLocation: Bengaluru or HyderabadDescription:1. Performing Timing closure of partitions at SoC level2. Providing placement feedback with respect to timing3. Reduction of clock ID, by analyzing necessary tap points4. Providing clock pulls and pushes to attain better QoR before going to ECOs to reduce leakage/utilization impact5. Fixing setup, Hold, TDRCs, Noise through ECOsShould have hands on tolls knowledge in:HDL’s: Verilog, VHDLEDA Tools: PTSI, Tempus, Tweaker, ICC2, Innovus, DCG/DCTScripting Languages: Exposure to Perl, Shell, Tcl, MakefileOperating Systems: Windows, Linux